CACHE COHERENCE SOLUTION UPDATE
CACHE COHERENCE SOLUTION UPGRADE
CACHE COHERENCE SOLUTION FULL

Kaxiras, S., Young, C.: Coherence communication prediction in shared-memory multiprocessors.

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303–313 (1996)Ĭheng, L., Carter, J.B.: Extending cc-numa systems to support write update optimizations.

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CACHE COHERENCE SOLUTION UPGRADE

IEEE Computer Society Press Los Alamitos, CA, USA (2002)Īcacio, M.E., González, J., García, J.M., Duato, J.: The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors. In: Proceedings of the 2002 ACM/IEEE Conference on Supercomputing, pp. NAS Parallel Benchmarks: OpenMP version developed by the Omni group Īcacio, M., González, J., García, J., Duato, J.: Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.

In addition, the proposed interconnection resource aware mechanism is proven to perform well under varying interconnection utilizations.

Results showed that the proposed mechanisms reduce cache-to-cache sharing misses up to 48 % and speed up application performance up to 34 %. Performance analysis is presented on a set of scientific applications from the SPLASH-2 and NAS parallel benchmark suites. Experimental evaluations, conducted on a tiled-CMP via full-system simulation, were used to assess the performance from our proposed dynamic hybrid protocols. Secondly, we extend this adaptive protocol with an interconnection resource aware mechanism. However, adaptively, it can push updates to potential consumers based on observed producer-consumer sharing patterns. The proposed protocol is based on a write-invalidate scheme. First, we propose an adaptive hybrid protocol to reduce coherence misses observed in write-invalidate based protocols. This paper presents two mechanisms to design efficient and scalable cache coherence protocols for CMPs. This is especially true under producer-consumer sharing patterns that can become a performance bottleneck as the number of cores increases. Also, contemporary cache coherence protocols use invalidate schemes that are known to generate a high number of coherence misses. Chip Multiprocessors (CMPs) have different technological parameters and physical constraints than earlier multi-processor systems, which should be taken into consideration when designing cache coherence protocols.

Cache coherence solution